1. Field of the Invention
The present invention relates to a digital phase locked loop circuit which employs digital processing elements to achieve the phase locked looping function. More particularly, the present invention relates to digital phase locked loop circuit which is well adaptable for reading out digital signals from a transmission system, for example, when the digital signal is reproduced in a recording/reproduction apparatus or when the digital signal is received in the data transmission system.
2. Description of the Related Art
There has been known a magnetic recording/reproduction apparatus of the type using magnetic recording medium, such as a magnetic tape or a magnetic disk, for digital signal recording and reproduction. In this type of the apparatus, to discriminately reproduce the original digital signal from the signal as read out of the recording medium, a clock signal must be used whose frequency corresponds exactly to the bit rate of the read out signal. To obtain such a clock signal, a phase locked loop circuit (PLL) is generally used to pick up it from the read out signal. The conventional PLL circuit has been of the analog type using, for example, a voltage controlled oscillator.
Magnetic recording/reproduction apparatuses operating at low data rate have been proposed. An exemplar of such apparatuses is a multi-track digital audio tape recorder of the stationary head type, which is now under development. For example, a digital PLL circuit for use in such apparatuses is disclosed by Junkichi Sugita et al., in their Japanese patent Disclosure No. 59-92410, and this digital PLL circuit is suitable for IC (integrated circuit) fabrication. Substantially the same technique as that of the above patent gazette is also proposed by Junkichi Sugita et al., "A Data Detection Method for a Stationary Head Digital Tape Recorder", IEICE Technical Report, EA82-59, pp. 33-40, 1982, and by Tetsuo Iwaki et al., "A Stationary Head Digital Audio Tape Recorder", IEICE Technical Report, EA86-9, pp. 41-48, 1986.
A block diagram shown in FIG. 1 schematically represents a configuration of the conventional digital PLL circuit disclosed in the above patent gazette by Sugita et al. A waveform shown in FIG. 2 is useful in explaining the operation of the FIG. 1 circuit.
In FIG. 1, a reproduced signal Rs is applied to input terminal 100. The reproduced signal Rs, an analog signal, has a history that in a magnetic recording/reproduction apparatus, a signal read out by a reproduction head (not shown) is amplified by a preamplifier, and is wave-equalized by an equalizer circuit. When the channel data rate of the recorded and reproduced signal is f bit/sec, 2f Hz or more suffices for the sampling frequency. Also in FIG. 1, the sampling frequency in A/D converter 101, which is for A/D converting the reproduced signal Rs, is selected to be two times the channel data rate. The sampling frequency is determined by a sampling clock signal derived from sampling clock generator 102. The signal Rs applied to input terminal 101 is sampled and converted into discrete values S.sub.i (i=1, 2, . . . ), or a series of digital data S.sub.1, S.sub.2, S.sub.3, . . . , S.sub.i, . . . as shown in FIG. 2. The data S.sub.i is output in parallel from A/D converter 101, each consisting of M bits (M=positive integer). In the illustration of FIG. 1, the output of A/D converter 101 is illustrated by a single line, for simplicity. The digital data Si is applied to D-type flip-flop (FF) 103, phase operation circuit 104 and zero-cross detector 105. FF 103 delays digital data Si by one sampling period. The output signal from D-type FF 103 is applied to phase operation circuit 104 and zero-cross detector 105. When a zero-cross point exists between sampling points S.sub.i and S.sub.i+1, phase operation circuit 104 calculates a phase difference .theta..sub.i between the zero-cross point and the sampling point of data S.sub.i+1 by using the input data S.sub.i and S.sub.i+1. More specifically, for the calculation, the curve ranging between points S.sub.i and S.sub.i+1 is linear approximated, and the phase angle of 360.degree. is expressed by 2.sub.n. That is to say, the circuit 104 operates the following relation ##EQU1## where .vertline.S.sub.i .vertline. and .vertline.S.sub.i+1 .vertline. are absolute values of data S.sub.i and S.sub.i+1. Zero-cross detector 105 detects the zero-cross point between the successive sampling points. The detector 105 decides that when the signs of the successive data, for example, S.sub.i and S.sub.i+1 are different, the zero-cross point exists between them. The output data signals from phase operation circuit 104 and zerocross point detector 105 are respectively applied to FFs 106 and 107, and latched therein. The data signal output from FF 106 and representing the phase angle .theta..sub.i in formula (1), is applied to subtractor 108. Subtractor 108 subtracts the output data signal .theta..sub.0 of adder 109 from .theta..sub.i. The data signal from subtractor 108 is applied to coefficient multiplier (referred to as a K-multiplier) 110. The K-multiplier 110 multiplies the received data signal by coefficient K(0&lt;K .ltoreq.1), and produces data signal represented by K(.theta..sub.i -.theta..sub.0). The data signal of K(.theta..sub.i -.theta..sub.0) is applied to AND gate 111. AND gate 111 is enabled by the signal from D-type FF 107, and allows the K(.theta..sub.i -.theta..sub.0) data signal to pass therethrough. When the zero-cross point is detected, since the .theta..sub.i of formula (1) represents the phase of data S.sub.i+1, AND gate 111 is enabled and the output data K(.theta..sub.i -.theta..sub.0) of multiplier 110 applied to adder 112. When the zero-cross point is not detected, since the .theta..sub.i of formula (1) does not represent the phase of data S.sub.i+1, AND gate 111 is disabled and 0 is applied to adder 112. Thus, a circuit section including subtractor 108, multiplier 110 and AND gate 111 functions like the phase comparator and the loop filter of the normal analog PLL circuit.
Adder 112 adds the data output signals from AND gate 111 and adder 109, and applies the addition result to FF 113. The output data signal from FF 113 is supplied to adder 109. Adder 109 also receives fixed data of 2.sup.n-1 from 2.sup.n-1 generator 114. Another circuit section made up of adders 109 and 112, D-type FF 113, and 2.sup.n-1 generator 114 functions like the voltage controlled oscillator of the analog PLL circuit. This circuit section operates such that the phase of the output signal of D-type FF 113 rotates 360.degree. at the frequency, which is 1/2 the sampling frequency of sampling clock generator 102, viz., equal to the channel data rate, and that the phase of that output signal is controlled by the input signal of AND gate 111 to adder 2. The clock signal of sampling clock generator 102 is applied to D-type FFs 103, 106, 107 and 113. The digital PLL circuit, thus arranged, includes both elements serving as a phase comparator and a loop filter and elements serving as a voltage-controlled oscillator, and therefore produces a signal which is phase-locked with the digital data output from A/D converter 101. The signal delay of this digital PLL circuit is a total of the delays of adder 109, subtractor 108, multiplier 110, AND gate 111, adder 112, and D-type FF 113. The upper operating frequency of the PLL circuit is limited by the delay time of the PLL. One may make the speed-up of the PLL circuit in such a way that the coefficient K of K-multiplier 110 is 1/2l (l=positive integer) and the delay time of multiplier 11 is zeroed by digit shifting, and the inversion of the most significant digit is substituted for adder 109 and 2.sup.n-1 generator 114. In this case, even if the improved PLL circuit is constructed with the present TTL IC, with n=8, the upper limit of the operating frequency of that circuit is at most 30 MHz for the sampling frequency. Accordingly, the digital PLL circuit based on the present TTL is applicable only for the magnetic recording/reproduction apparatus whose channel data rate is 15 M bits/sec or smaller.
In the conventional digital PLL circuit of FIG. 1, the loop filter substantially consists of only K-multiplier 110. Therefore, the loop gain of the circuit is small, and hence a stationary phase error is large. To reduce the stationary phase error, a leak integrator may be used for K-multiplier 110. Use of the leak integrator increases the loop gain in low frequency regions. However, the leak integrator complicates a circuit arrangement of the loop filter included circuit. This results in increase of the signal delay in the phase locked loop, and decrease of the operating frequency.
As described above, the prior digital PLL circuit has the following problems.
(1) Since the tolerable channel data rate must be set to be low, the PLL circuit is applicable for only those magnetic recording/reproduction apparatuses operating at low channel data rate.
(2) To increase the operating frequency, one may simplify the loop filter. This approach, however, results in increase of the stationary phase error. To cope with this phase error increase, one may modify the PLL circuit to increase the loop gain in low frequencies. This additional approach brings about a complicated circuit arrangement, and hence reduces the operating frequency of the PLL circuit.